Synopsys Design Compiler Tutorial 2021 Better

Design Compiler is "constraint-driven." If you don't tell it how fast the design should be, it won't optimize for speed. These are typically saved in a file. The Clock:

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set_clock_latency -source -max 0.200 [get_clocks core_clk] set_clock_latency -max 0.100 [get_clocks core_clk] Design Compiler is "constraint-driven

# Define the symbol library (for schematics in GUI) set symbol_library slow.sdb synopsys design compiler tutorial 2021